Intest security circuit for boundary-scan architecture
US6499124B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 6, 1999 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A security circuit for an IEEE Standard 1149.1 compliant PLD that is controlled by a security bit or bits programmed when the PLD is incorporated into a final product. The security circuit includes a switch connected directly or indirectly into the Boundary-Scan Register (BSR) chain of the PLD. The security bit applies a control signal to the switch such that test data signals generated during INTEST procedures are either passed through the switch, or blocked by the switch. For example, when the Boundary-Scan architecture of the PLD is set for INTEST procedures when the security bit is set in a first programmed state, the logic gate passes test data from an input terminal to an output terminal. Conversely, when the security bit is set in a second programmed state, the logic gate masks the test data values received at the input terminal (i.e., the shifted test data is blocked).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.