Alternating reference wordline scheme for fast DRAM
US6501675B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | May 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4099
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time. The write-back of the reference cells can be hidden since an alternate cell is available for next cycle's reference bitline generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.