Channel write/erase flash memory cell and its manufacturing method
US6501685B2 · kind B2 · utility
28Cited by
9References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2002 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jan 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pseudo-dynamic operating method and a flash memory cell capable of performing this operating method are disclosed. A parasitic capacitor near the drain terminal of the flash memory can be charged in few microseconds during operation. Interference generated between the floating gate and the source is avoided by using a first oxide layer which is thicker at the interface between floating gate and source and thinner near central part under stacked gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.