Circuit and method for stress testing a static random access memory (SRAM) device
US6501692B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Sep 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stress test circuit and method for static random access memory (“SRAM”) cells of an SRAM device are disclosed. The stress test component has a resistance element and a switch component to electrically couple the resistance element between a bit line and complementary bit line of an SRAM cell storing a digital value. Stress test component is activated to electrically couple the resistance element to the bit line and complementary bit line. An electrical path is created causing a voltage on an SRAM circuit path maintaining the digital value to be pulled in one direction by a stress current. The electrical path causes another voltage on another SRAM circuit path maintaining a complementary digital value to be pulled in an opposite direction by the stress current. The SRAM cell is then read to determine whether the digital value has changed state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.