Structure and method for hiding DRAM cycle time behind a burst access
US6501698B1 · kind B1 · utility
15Cited by
12References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.