Memory test circuit
US6502214B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test circuit in a test mode divides a plurality of mats forming a memory and coupled with identical global input/output lines into even and odd-numbered mats and simultaneously activates the even or odd-numbered mats. The memory test circuit sequentially amplifies the activated even or odd-numbered mats, and simultaneously compares the amplified mats in a latch unit, which decreases the memory test time. The memory test circuit can further include a mat controlling unit for dividing a plurality of mats into even and odd-numbered units and simultaneously controlling the even or odd-numbered mats, a mat switch controlling unit for controlling a plurality of mat switches to be sequentially operated, a main amp controlling unit for controlling a plurality of main amps to be sequentially operated, and a latch unit for latching data amplified by the plurality of main amps to be simultaneously outputted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.