Deferred correction of a single bit storage error in a cache tag array
US6502218B1 · kind B1 · utility
17Cited by
6References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus defer correction of an error in a tag entry of a cache tag array. An address of requested data, including an address tag field, can be received by a cache. A first hit indication based at least in part on a comparison of the address tag field and a first tag entry can be generated and result in outputting of a first data entry of a data array. An error in the tag entry can be detected, and the first data entry can be disregard based at least in part on the detected error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.