Method for concurrently forming an ESD protection device and a shallow trench isolation region
US6503793B1 · kind B1 · utility
14Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Aug 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The invention comprises concurrently forming an isolation trench in an active region and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.