Process to increase reliability CuBEOL structures
US6503834B1 · kind B1 · utility
28Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/288
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.