Method to create EEPROM memory structures integrated with high performance logic and NVRAM, and operating conditions for the same
US6504207B1 · kind B1 · utility
34Cited by
11References
10Claims
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Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Aug 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.