Method and apparatus for enhanced SOI passgate operations
US6504212B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Feb 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle. The method for implementing enhanced silicon-on-insulator (SOI) passgate operations can be used with N-channel or P-channel implementations as well as with a combination of N-channel and P-channel devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.