Passive semiconductor device mounted as daughter chip on active semiconductor device
US6504227B1 · kind B1 · utility
43Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/957
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.