Device and method for checking integrated capacitors
US6504380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/78
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device includes a capacitive structure including an input node and n output nodes, r integrated capacitors connected in series between two adjacent nodes, an integrated capacitor connected between the input node and ground, an integrated capacitor connected between the nth output node and ground, and r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch may include r+1 series-connected integrated capacitors. Furthermore, the integrated capacitors of the capacitive structure are theoretically identical. The device may also include a charge source for charging each node of the capacitive structure. Additionally, a measurement circuit may measure the charge at each of the nodes of the structure, and a comparison circuit may compare each measured nodal charge value with a theoretical nodal charge value while taking into account a predetermined nodal tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.