Clock distribution for improved jitter performance in high-speed communication circuits
US6504415B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Aug 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In many electronic systems, it is common to communicate data from a transmitter in one device to a receiver in another. Accurate communications requires use of several matched clock signals. Mismatches in these clock signals cause transmitters to add “jitter” to transmitted data or receivers to be more intolerant of jitter in received signals, increasing the chances of mis-interpreting the data. Accordingly, the inventors devised an exemplary clock-distribution method which entails generating a base set of matched clock signals, deriving at least two separate sets of matched clock signals from the base set, and distributing one of the sets of clock signals to a set of matched components in a circuit and the other set of matched clock signals to a different set of components in the same circuit. The clock signals driving the matched components are isolated from mismatched aspects of the other components, and thus exhibit better matching. This method improves the accuracy of high-speed receivers, transmitters, transceivers, and other communications circuits that use it.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.