High-density low-cost read-only memory circuit
US6504746B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | May 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49175
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-density low-cost read-only memory circuit is disclosed. Within the memory circuit, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array. The passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.