Semiconductor memory device
US6504755B1 · kind B1 · utility
59Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is constituted by forming two types of insulation films on the channel of an MOS transistor on which a vertical type another MOS transistor using the control gate of the MOS transistor as a substrate is stacked. Thus, a non-volatile semiconductor memory device small in size, having high reliability, high density, excellent fatigue and a random access function can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.