Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding
US6504758B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Sep 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.