Generating an instance-based representation of a design hierarchy
US6505327B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Apr 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node's siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell. If the changes result in a new node for which no instance has been created, the system creates a new instance for the node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.