Method of forming IC package having downward-facing chip cavity
US6506632B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The pat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.