Method of fabricating a multi-chip module package
US6506633B1 · kind B1 · utility
35Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.