Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
US6506668B1 · kind B1 · utility
28Cited by
21References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Jun 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1089
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming interconnects on a semiconductor chip is disclosed which comprises the steps of: depositing a barrier layer and a copper seed layer on the semiconductor chip; depositing on the copper seed layer an enhancement layer; annealing the semiconductor chip a first time after the copper seed layer and the enhancement layer are deposited to form an annealed layer; electroplating a copper layer on the semiconductor chip; and annealing the semiconductor chip a second time after the copper layer is deposited on the annealed layer to form an annealed copper conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.