Structure of a CMOS image sensor
US6507059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
Abstract
A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.