Poly-poly/MOS capacitor having a gate encapsulating first electrode layer

US6507063B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Douglas D. Coolbaugh · Highland, US
• James S. Dunn · Jericho, US
• Stephen A. St. Onge · Colchester, US

Key dates

• Filing date: Apr 17, 2000
• Grant date: Jan 14, 2003
• Expiry date: Apr 17, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/212

Abstract

A stacked Poly-Poly/MOS capacitor useful as a component in a BiCMOS device comprising a semiconductor substrate having a region of a first conductivity-type formed in a surface thereof; a gate oxide formed on said semiconductor substrate overlaying said region of first conductivity-type; a first polysilicon layer formed on at least said gate oxide layer, said first polysilicon layer being doped with an N or P-type dopant; a dielectric layer formed on said first polysilicon layer; and a second polysilicon layer formed on said dielectric layer, said second polysilicon layer being doped with the same or different dopant as the first polysilicon layer.