Fully silicide cascaded linked electrostatic discharge protection
US6507090B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
A method and a structure of for an Electro Static Discharge (ESD) device that is silicided. There are three preferred embodiments of the invention. The first embodiment has a N/P/N structure. The emitter, the collector and the substrate form a parasitic transistor and the substrate is connected to the p+ diffusion region. The emitter and the substrate act as a first diode D1 and the collector and the substrate act as a second diode D2. The second embodiment has a first N+ well between a second n+ (collector) region and a P+ base region. The Vt1 is controlled by the dopant profiles of the P+ base and the n− first well where they intersect. The third embodiment is similar to the second embodiment, but the n− well covers all of drain. A parasitic NPN bipolar transistor comprises: an emitter, a parasitic base and a drain. The emitter is formed by the first n+ region. The parasitic base is formed by the p-substrate. The collector is formed by the second n+ region and the first n− well. The Vt1 is controlled by the dopant profiles of the P+ base and the n− first well where they intersect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.