Circuit for the filtering of parasitic logic signals
US6507221B2 · kind B2 · utility
12Cited by
6References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Aug 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A filtering circuit includes circuits for delivering first and second ramp-shaped signals when a logic signal to be filtered changes values, and includes logic circuits each with a switching threshold, for receiving the ramp-shaped signals. A memory unit delivers an output signal having a first value when outputs of the logic circuits have a first pair of values, and delivers a second value when the outputs of the logic circuits have a second pair of values. The filtering circuit may be applied to the filtering of an external clock signal in serial type memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.