Integrated circuit memory chip for use in single or multi-chip packaging
US6507514B1 · kind B1 · utility
15Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Oct 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the control circuit portion is inactive. In a multi-chip packaged configuration, the control circuit serves to prolong the activation of the currently addressed memory chip, while delaying the activation of the memory chip which is to be addressed in the next memory address cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.