Circuital structure for programming data in a non-volatile memory device
US6507517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | May 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit structure for programming data in reference cells of an electrically programmable/erasable integrated non-volatile memory device includes a matrix of multi-level memory cells and a corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell is incorporated, along with other cells of the same type, in a reference cell sub-matrix which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix branch off to a series of switches which are individually operated by respective control signals REF(i) issued from a logic circuit with the purpose of selectively connecting the bit lines to a single external I/O terminal through a single addressing line of the access DMA mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.