Integrated circuit memory having column redundancy
US6507524B1 · kind B1 · utility
9Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array has memory elements arranged in rows and columns. Each column has a respective bit line. A plurality of bit line input-output nodes are each switchably coupled to either a respective one of the bit lines or another one of the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.