Column decoder circuit for page reading of a semiconductor memory
US6507534B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2001 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Mar 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column decoder circuit for page reading of a semiconductor memory includes a first level decoder stage, a second level decoder stage, and a plurality of bit selection stages, each comprising a plurality of selection branches; wherein each selection branch is connected to a respective input of a multiplexer and has a plurality of first level selector stages and a second level selector stage. Each second level selector stage comprises a first addressing selector for addressing a first group of bit lines. Each bit selection stage further comprises a second addressing selector for addressing a second group of bit lines, current and next page selectors for selecting one of the first and second groups of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.