Daniele Balluchi
98Patents
7h-index
38Co-inventors
72Inventor score
Filing activity: Feb 27, 2001 → May 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11036625B1 | Host-resident translation layer write command associated with logical block to physical address of a memory device | Physics | 17 | Active |
| US9734097B2 | Apparatuses and methods for variable latency memory operations | Physics | 12 | Active |
| US8504759B2 | Method and devices for controlling power loss | Physics | 11 | Active |
| US9685234B2 | Apparatuses and methods for performing multiple memory operations | Physics | 10 | Active |
| US6507534B2 | Column decoder circuit for page reading of a semiconductor memory | Physics | 9 | Expired |
| US10067890B2 | Apparatuses and methods for variable latency memory operations | Physics | 7 | Active |
| US9454310B2 | Command queuing | Physics | 7 | Active |
| US7154803B2 | Redundancy scheme for a memory integrated circuit | Physics | 7 | Expired |
| US10083751B1 | Data state synchronization | Emerging Cross-Sectional Technologies | 6 | Active |
| US8824235B2 | Controlling clock input buffers | Physics | 6 | Active |
| US8762656B2 | Temperature alert and low rate refresh for a non-volatile memory | Physics | 5 | Active |
| US11687273B2 | Memory controller for managing data and error information | Emerging Cross-Sectional Technologies | 4 | Active |
| US11335416B1 | Operational modes for reduced power consumption in a memory system | Physics | 4 | Active |
| US8543787B2 | Non-volatile memory circuit, system, and method | Emerging Cross-Sectional Technologies | 3 | Active |
| US10068649B2 | Apparatuses and methods for performing multiple memory operations | Physics | 2 | Active |
| US10649665B2 | Data relocation in hybrid memory | Physics | 2 | Active |
| US10430085B2 | Memory operations on data | Emerging Cross-Sectional Technologies | 2 | Active |
| US8825979B2 | Non-volatile memory circuit, system, and method | Emerging Cross-Sectional Technologies | 2 | Active |
| US10261876B2 | Memory management | Physics | 2 | Active |
| US10809942B2 | Latency-based storage in a hybrid memory system | Physics | 2 | Active |
| US10719248B2 | Apparatuses and methods for counter update operations | Emerging Cross-Sectional Technologies | 2 | Active |
| US10705963B2 | Latency-based storage in a hybrid memory system | Physics | 2 | Active |
| US10592427B2 | Logical to physical table fragments | Physics | 2 | Active |
| US11055000B2 | Apparatuses and methods for counter update operations | Emerging Cross-Sectional Technologies | 2 | Active |
| US12099457B2 | Controller for managing multiple types of memory | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.