Method for testing semiconductor wafers
US6507800B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Mar 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for identifying failure signatures of semiconductor wafers is disclosed. Testing for obtaining a first set of test data indicative of a failure signature is performed on a number of wafers having circuit patterns thereon. The test data is divided into a first subset of test data associated with a failure signature and a second subset of test data not associated with the failure signature. The set of test data is used to generate coefficients of a discriminant function. Testing is performed on a subsequently manufactured wafer to obtain a second set of test data. The discriminant function is applied to the second set of test data to obtain a discriminant value, and the wafer is identified as having the failure signature when the discriminant value is greater than or equal to a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.