L1 cache memory
US6507892B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 21, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive cache processes multiple access requests simultaneously by using separate queuing structures for data and instructions. The inventive cache uses ordering mechanisms that guarantee program order when there are address conflicts and architectural ordering requirements. The queuing structures are snoopable by other processors of a multiprocessor system. The inventive cache has a tag access bypass around the queuing structures, to allow for speculative checking by other levels of cache and for lower latency if the queues are empty. The inventive cache allows for at least four accesses to be processed simultaneously. The results of the access can be sent to multiple consumers. The multiported nature of the inventive cache allows for a very high bandwidth to be processed through this cache with a low latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.