Method and system for improving yield of semiconductor integrated circuits
US6507930B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jan 14, 2003 |
| Priority date | — |
| Expiry date | Sep 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system are disclosed for improving a yield of circuits produced from a semiconductor wafer. A plurality of design rules are established for designing a layout of the circuit within the wafer. A yield-limiting set of the plurality of design rules are selected. Adherence to each of the set of rules throughout all of the layout reduces the yield. For each one of the set of rules, a recommended value is determined. A percentage of occasions each one of the set should be exceeded within the layout is also determined. The layout is then designed so that each one of the set of the plurality of design rules meets or exceeds the recommended value more often than the percentage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.