Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
US6509267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76873
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a metal interconnect structure provides a conformal layer of barrier material, such as a nitride, within a patterned opening in a dielectric layer. The barrier material is deposited after the opening is etched to the dielectric layer, stopping on a diffusion barrier. A first layer of a metal barrier material, such as tantalum, is conformally deposited on the barrier material. A directional etch is performed that removes horizontal nitride and tantalum, leaving the nitride and tantalum on the sidewalls of the patterned opening. The barrier material prevents contamination of the dielectric layer from conductive material, such as copper, during the etching of the diffusion barrier overlying the conductive material, and during subsequent sputter etch cleaning. A thin, second metal layer is conformally deposited and forms a suitable barrier on the sidewalls of the opening, while providing low contact resistance between the second metal layer and the underlying substrate. The second metal layer serves as a nucleation step for electrolessly plating a copper seed layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.