Semiconductor memory device having capacitor protection layer and method for manufacturing the same
US6509601B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
A semiconductor memory device having a capacitor protection layer and a method for manufacturing the same. A capacitor of the semiconductor memory device is entirely covered with an encapsulating layer having a multi-layered structure. The encapsulating layer comprises at least a blocking layer and a capacitor protection layer, each of which is formed of different materials. The blocking is formed of a material capable of preventing a capacitor dielectric layer from volatilizing and/or capable of preventing a reaction between a material layer under the blocking layer and the capacitor protection layer. The capacitor protection layer is formed of a material layer capable of preventing diffusion of hydrogen into the capacitor dielectric layer. In addition, the semiconductor memory device may has a hydrogen barrier layer as another capacitor protection layer, between the capacitor and a passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.