Clock-synchronous semiconductor memory device
US6510101B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Jan 21, 2003 |
| Priority date | — |
| Expiry date | Oct 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array, a control section and latency setting circuit. The control section configured to receive a clock signal and a first control signal, and configured to output a plurality of the data in synchronism with the clock signal after the first control signal is asserted, output of the data beginning a number of clock cycles (latency N) of the clock signal (latency N being a positive integer ≧2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output. The latency setting circuit sets the latency N. The latency setting circuit includes at least one switch which permanently fixes a latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.