Plating method using an additive
US6511588B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2000 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Apr 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A plating method comprising using a plating solution containing an additive satisfying the following conditions:0.005×h2/w<D/&kgr;<0.5×h2/w,and0.01≦&THgr;≦0.7wherein D is a diffusion coefficient of the additive; &kgr; is a surface reaction rate of adsorption or consumption of the additive; h is a height of a trench or hole; w is the width of the trench or the radius of the hole; and &THgr; is a ratio of (plating film growth rate in the presence of additive)/(plating film growth rate in the absence of additive), is suitable for forming the plating metal in the trench or hole having the width of 1 &mgr;m or less (trench) or the radius of 1 &mgr;m or less (hole) without generating voids, and particularly suitable for producing semiconductor devices, which can have a multilayer structure of copper wiring layers formed on a semiconductor substrate by using the plating conditions, wherein at least one layer of copper wiring layers is plated in different conditions from the rest of the copper wiring layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.