Method for making FET gate oxides with different thicknesses using a thin silicon nitride layer and a single oxidation step

US6511887B1 · kind B1 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Mo Yu · White Plains, US
• Syun-Ming Jang · Baoshan, TW

Key dates

• Filing date: Jun 19, 2000
• Grant date: Jan 28, 2003
• Expiry date: Jun 19, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

A method for making a dual-gate oxide field effect transistors is achieved. The method utilizes a patterned thin silicon nitride layer and a single rapid thermal oxidation step to form a thicker gate oxide for memory and peripheral circuits while forming a thin nitrogen rich gate oxide for high-performance logic circuits. After forming STI around the logic and memory call areas and removing any native oxide, a thin CVD silicon nitride layer is deposited. The Si3N4 is patterned to leave portions over the logic device areas. A single rapid thermal oxidation process is performed to grow a thicker gate oxide on the exposed memory areas while concurrently the Si3N4 is slowly converted to a nitrogen-rich oxide and forms a thinner gate oxide on the logic device areas. The thinner nitrogen-rich gate oxide also retards boron diffusion to make more stable devices.