Method and structure for improving hot carrier immunity for devices with very shallow junctions
US6512273B1 · kind B1 · utility
50Cited by
8References
10Claims
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Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
An integrated circuit CMOS structure and method for forming the structure provides gate sidewall spacers which are independently optimized for the n-channel and p-channel devices to improve hot-carrier lifetime while maintaining high drive currents. This is accomplished by providing polysilicon spacers for the n-channel devices and silicon nitride spacers for the p-channel devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.