Configurable memory for programmable logic circuits
US6512395B1 · kind B1 · utility
55Cited by
33References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a memory device and a programmable logic device. The memory device may be configured to (i) connect to a first bus and a second bus and (ii) operate in one or more modes in response to one or more control signals. The programmable logic device may be configured to generate the control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.