Circuit structures and methods for high-speed low-power select arbitration
US6512397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Aug 20, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue. The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.