Non-volatile memory cell having channel initiated secondary electron injection programming mechanism
US6512700B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell. In an illustrative embodiment, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts, thus alleviating program disturb problems that can result, e.g., when the drain-to-substrate voltage is applied to multiple columns of an array of cells that are programmed one row at a time. The memory cell is programmed by channel initiated secondary electron (CHISEL) injection of charge onto the floating ga…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.