Semiconductor memory device operating with low power consumption
US6512715B2 · kind B2 · utility
37Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2001 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Nov 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.