Semiconductor memory device having a relaxed pitch for sense amplifiers
US6512717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.