Dual burst latency timers for overlapped read and write data transfers
US6513089B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2000 |
| Grant date | Jan 28, 2003 |
| Priority date | — |
| Expiry date | May 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.