Process for the double-side polishing of semiconductor wafers and carrier for carrying out the process

US6514424B2 · kind B2 · utility

Assignee

• Wacker Siltronic Gesellschaft Fur Halbleitermaterialien AG · DE

Inventors

• Guido Wenski · Burghausen, DE
• Gerhard Heier · Burghausen, DE
• Wolfgang Winkler · Dresden, DE
• Thomas Altmann · Burghausen, DE

Key dates

• Filing date: Apr 4, 2001
• Grant date: Feb 4, 2003
• Expiry date: Aug 1, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02024
• WIPO field: Machine tools
• WIPO sector: Mechanical engineering

Abstract

A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.