Method for manufacturing contacts for a Chalcogenide memory device
US6514788B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | May 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8418
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing contacts for a Chalcogenide memory device is disclosed. A via is initially formed within a first oxide layer on a substrate. A conductive layer is then deposited on top of the first oxide layer. A second oxide layer is deposited on the conductive layer. Subsequently, the second oxide layer and the conductive layer are then removed such that the remaining portion of conductive layer within the via flushes with a surface of the first oxide layer. A third oxide layer is deposited on the conductive layer, and the first and second oxide layers. A pattern is formed to remove third layer so that the pattern opens orthgonally across and exposes the conductive layer. Next, a nitride layer is deposited on the third oxide layer, the conductive layer, and the first and second oxide layers. The nitride layer conforms with the contour of the third oxide layer. After directionally removing the nitride layer to form a spacer at the exposed edge of the third oxide layer, the third oxide layer is removed to expose the spacer. The conductive layer is then etched to remove a portion of the conductive layer not underneath the spacer. The portion of the conductive layer undern…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.