Method of using controlled resist footing on silicon nitride substrate for smaller spacing of integrated circuit device features
US6514874B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | Jun 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings. These footings reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.