Semiconductor device manufacturing method to reduce process induced stress and crystalline defects
US6514885B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 3, 2000 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | May 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To reduce dislocations produced in the formation of shallow trench isolation regions in a semiconductor substrate, the semiconductor substrate is annealed in N2 ambient pressure with an O2 partial pressure of less than about 10−4 at a temperature between about 950 C.° and about 1055 C.°. In addition, a method to reduce crystalline defects in semiconductor manufacturing in which a metal is deposited on an insulator to form metal silicide is provided. The method provides for etching the insulator to create an overhang by an amount equal to at least one half of the thickness of the metal, thereby creating a void between the surface of the semiconductor substrate and the insulator. The metal is deposited on the first insulator and on the surface of the semiconductor substrate and the semiconductor substrate is heated thereby forming metal silicide on the surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.