Semiconductor device with FET MESA structure and vertical contact electrodes
US6515348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2001 |
| Grant date | Feb 4, 2003 |
| Priority date | — |
| Expiry date | May 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6). (FIGS. 12 and 13)
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.